Download A Guide to Analog Asics by Paul M. Brown Jr. PDF

By Paul M. Brown Jr.

Software particular built-in circuits (ASICs), either analog and electronic, became usual approach point bulding blocks. ASIC owners have tried to supply instruments that they desire will let particularly green IC designers (i.e. structures engineers) to layout subtle customized built-in circuits. This philosophy has been extra winning in electronic know-how than in analog. considerably extra paintings is concerned with analog layout and much fewer automatic instruments can be found. nearly each analog ASIC seller bargains various semiconductor applied sciences, device units, documentation (usually missing intimately and never delivering the correct heritage and guidelines), and ranging degrees of engineering aid. the result's that many engineers who might use analog ASICs lack the technical details to take action. they aren't certain while customized analog ICs are low-cost or which seller will top serve their wishes. furthermore, many engineers would not have enough analog layout event, specially with built-in circuits. Consqeuently, many that may benefit from analog ASIC expertise don't use it whereas others have undesirable reports which can have simply been shunned.

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0 Introduction Component parameters and specifications given in this book are meant to be representative and are used for illustration. Current vendor data should be consulted before any detailed design work is started. IC manu­ facturers change their processes from time to time to improve perfor­ mance and production yields. If you are considering multiple sources for a custom IC, it is wise to review the design data from the alternate manufacturer(s) prior to beginning detailed design work. A little re­ search up front will help you identify and avoid vendor dependencies.

The emitter-to-collector current flow is lateral, as the name im­ plies. The purpose of the buried layer in a lateral pnp is to keep carriers from being collected by the reverse-biased, epi-substrate junction. Some collection, however, does occur at the epi-isolation junction. For this reason substrate contacts should be made in relatively close proximity to lateral pnps to prevent substrate currents from flowing long dis­ tances. Since the transistor action is lateral, the effective emitter area is not the area of the diffusion (as in the case of an npn) but rather the area around the periphery of the emitter.

This way, when a customer brings in a circuit ready for integration, all of the processing except for the last few steps is already completed. This is why semicustom prototype turn­ around is so fast. 3 Semiconductor Processing 29 Contact opening Oxide ( S i 0 ) 2 Figure 2-15 Contact etch. The metal mask defines the metal areas that must remain to prop­ erly connect the desired circuit. At this point, the chip is like an unetched PC board with the components already stuffed. A photoresist, masking, and etch process removes the undesired metal, leaving the final circuit connected.

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